Methods of forming CMOS integrated circuits may include processing steps that influence charge carrier mobility within PMOS and NMOS transistors. Some of these processing steps may increase charge carrier mobilities in the channel regions of the PMOS and NMOS transistors by stressing the channel regions. For example, the mobilities of the N-type charge carriers (i.e., electrons) within the channel regions of NMOS transistors may be increased by adding a tensile stress to the NMOS channel regions and the mobilities of the P-type charge carriers (i.e., holes) within the channel regions of PMOS transistors may be increased by adding a compressive stress to the PMOS channel regions.
Unfortunately, conventional semiconductor processing techniques typically do not yield NMOS and PMOS transistors having sufficiently stressed channel regions. For example, conventional semiconductor processing techniques may result in PMOS transistors having highly compressively stressed channel regions, but these techniques may result in NMOS transistors having channel regions with insufficient tensile stresses therein.